Author: Kevin Slavinec
Mentor: izr. prof. dr. Matej Rojc
Co-mentor: izr. prof. dr. Anton Pleteršek
External co-mentor: dr. Iztok Bratuž
Program: Level 2 study, Electrical Engineering, course Electronics
Date: August, 2022
DKUM: KEVIN SLAVINEC
Abstract
This master thesis describes the integration and verification of a processor core with NFC interface. The basic operation of each integration unit, the operation of the NFC interface and processor core is presented. In the integration part, we designed digital blocks for communication between the NFC interface and processor core via AHB and APB data buses. We rearranged the memory architecture of the processor core for digital part of the NFC interface – the registers and the internal memory. In order to verify the system, we developed firmware for the processor, through which the NFC interface is controlled. We prepared a test bench for FeliCa protocol, which was used to simulate the presence of a card on the antenna pins of the SoC. With the successfully received packet in the processor core, we verified APB and AHB data bus connection between the processor core and NFC interface. We also made a test bench for the SWD protocol, which is used for debugging, loading program code into RAM, and executing the program code from RAM.
Radio Frequency Identification
RFID is a form of wireless communication that involves the use of an electromagnetic or electrostatic connection in the high frequency part of the electromagnetic spectrum, to uniquely identify an object, animal or person. RFID devices are mainly divided into two groups. The first group consists of detectors and a reader, the main purpose of which is to generate a radio frequency field and establish communication. The second group consists of tags and cards, the main purpose of which is to receive commands sent by readers and to respond and store data. This group is also divided into passive, active and semi-passive elements. Each RFID system consists of three components: an antenna, a transmitter and a transponder. When the receiving antenna and transceiver are combined, they are called an RFID reader or interrogator. An RFID reader is a device connected to a permanent power source that can be portable or permanently attached. It uses radio waves to transmit signals that activate a transponder, also called a tag or badge. When the tag is activated, it sends a modulated wave back to the antenna, where the wave is converted into data via demodulation. Communication is based on the master/slave principle, where the master initiates communication and issues commands, while the slave can only respond. In classical RFID communication, the interrogator assumes the role of a master, and the card the role of a slave.
Processor core
The integration of the processor core into the NFC interface is based on the connections of the advanced high-performance bus AHB, the advanced peripheral bus APB and signals that enable various functions and states of the NFC interface. In addition to the processor core, we also need memory, which takes care of storing program code and data. The resulting equipment integration system also requires other mandatory functions and signals, including a clock for synchronous data transmission, a reset circuit for system initialization, and a power and interrupt line. For the processor core, we chose Cortex-M0+ manufactured by ARM. The Cortex-M0+ processor is a configurable, multi-level 32-bit RISC processor. It has an AMBA AHB-Lite interface, an interrupt controller (NVIC), a single-cycle I/O interface, a memory protection function, and a hardware debugger. Registers are used to store and perform operations, which serve as sources and destinations for data. In modern processors there can be 16, 32 or more. Depending on the architecture of the processor, there may be several groups of registers. To write or read the contents of these registers, access is performed via one or more internal data buses.
Integration of the processor core with the NFC interface
The NFC interface consists of a digital and analog part. In the analog part, there are blocks that take care of the correct reception and transmission of different types of modulations. This part contains various modulators, demodulators, power connectors and antenna connectors, through which the signal that we want to modulate or demodulate is transmitted or received. In the digital part, there is data control for encoding, decoding, registers through which we set the desired modulations, the states of the NFC interface, regardless of whether the NFC is powered by a battery or only via the field accepted by the NFC interface. The digital part also takes care of various functions, and various interrupts that take care of waking up the processor from sleep and various control blocks for the analog part. AHB and APB data buses are also located in the digital part. The AHB data bus takes care of communication with the internal memory of the NFC interface. The latter has its own memory, into which it writes data after reception, and in the case of transmission, it reads data from the memory, which it must transmit via the analog part, where it is then modulated according to the protocol. The APB data bus provides access to individual registers of the NFC interface, where protocols and interrupts are set. To connect the NFC interface to the processor core, we had to create a new AHB bus architecture, where we defined the individual locations of the system components. We connected the ROM to the buses, in which we store the program code in the initial stages of development, the RAM used for data storage, the default slave, two GPIO interfaces, the RAM NFC interface and the AHB-APB bridge. Signals for controlling the NFC interface were also connected to the GPIO interface.
HORIZON-MSCA-2021-BosomShield